It is highly recommended that the PCB designer/SMT process engineer obtain the complete IPC 7351 standard ( IPC) Tomb Stoning / Chip Movement: A summary of the IPC land pattern design recommendations for solder reflow and solder wave processes are listed in table below. The standard also contains an excellent analysis of solder joints and their relation to component, PCB, and placement tolerances. This standard presents industry consensus on optimum dimensions based on empirical knowledge of fabricated land patterns. The Institute for Interconnecting and Packaging Electronic Circuits (IPC) has developed and published IPC 7351 "Surface Mount Design and Land Pattern Standard". IPC 7351 Land Pattern Guidelines:Īppropriate pad design, solder application, and component orientation are all ingredients of a quality, defect-free soldering process.
In the event that a soldering iron must be employed the following precautions are recommended. Attempts to speed this cooling process or immediate exposure of the circuit to cold cleaning solutions increase the possibility of thermal shock cracking of the ceramic capacitor.Ĭeramic capacitor attachment with a soldering iron is discouraged due to the inherent process control limitations. Never contact the capacitor with the iron tipĪfter the solder reflows properly the assembly should be allowed to cool gradually, again maintaining the thermal gradient of 3° C / sec.Preheat circuit and capacitors to within 100° C of soldering temperature.Land patterns should be 2/3 narrower than the chip width to control solder fillet volume and minimize local Coefficient of Thermal Expansion (CTE) mismatch between the capacitor, solder and board.Ĭeramic capacitor attachment with a soldering iron is discouraged due to the inherent process control limitations. Cool down after solder wave requires rate control < 2° C / sec. Wave soldering is not recommended for ceramic MLCCs larger then 1206 and thicker than 1.2mm size due to the incompatibility of the chip's mass with the steep temperature gradient typically present in this process. And the maximum tie at peak temperature should not be greater than 5 seconds. It is important that the preheat temperature is within 150° C of the solder wave peak temperature.
#SOLDER REFLOW TEMPERATURE FREE#
Wave soldering can be utilized for lead free assembly, but the preheat requirements generally make this process very difficult to accomplish as peak temperatures may reach 260° C. Solders typically utilized in the solder wave have melting points between 179° C and 227° C. Recommended temperature profiles for reflow soldering are shown in Table 1 and Figure 1 from J-STD-020C Use of thermal profiling is advised for accurate characterization of circuit heat absorption and maximum component temperature conditions that occur during the soldering process. Based on these facts reflow temperatures between 210 to 260° C should be adequate in most circumstances. Activation of rosin fluxes occurs at about 200° C. Solders typically utilized in SMT Reflow Solders have melting points between 179° C and 217° C. Temperature change should be distributed as evenly as possible throughout large capacitor bodies as applying heat or cold to a localized spot within device may result in thermal gradients great enough to cause cracking. The circuit assembly should be preheated as shown in the recommended profiles at a rate of 1.0 to 3.0° C per second to within 75 to 125° C of the maximum soldering temperature. Proper preheating is essential to prevent thermal shock cracking of the capacitor. Note 1: All temperature refer to topside of the package, measured on the package body surface. Time within 5° C of actual Peak Temperature (tp)
The attached diagram from J-STD-020C shows both standard and lead free profiles. Higher temperatures are now required for "Lead Free" solder profiles. These large parts require more care during installation than smaller surface mount devices. Attention to these details will aid in the successful use of the inherently reliable multilayer ceramic capacitor.Ĭeramic capacitors larger then EIA size 1812 are known to be very susceptible to thermal shock damage due to their large ceramic mass.
Once initiated, the cracks can grow with time and cause latent failures. The problem is further complicated by the fact that these micro-cracks may not be initially detectable by standard electrical testing. These guidelines are emphasized because cracking or other damage caused by handling or thermal shock is not very small (micro-cracks) and can occur under the terminations where even high magnification cannot detect them. Soldering temperature profiles used must provide adequate temperature rise time and cool-down time to prevent damage due to thermal shock.
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